Bifacial solar cells with back surface doping

ABSTRACT

A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes an active region located on the front surface of the substrate, formed for example by a phosphorous diffusion step. The back surface includes a doped region, the doped region having the same conductivity as the substrate but with a higher doping level. Contact grids are formed, for example by screen printing. Front junction isolation is accomplished using a laser scribe.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of U.S. patent application Ser. No.12/456,404, filed Jun. 15, 2009, which claims the benefit of the filingdate of U.S. Provisional Patent Application Ser. No. 61/215,199, filedMay 1, 2009, the disclosure of which is incorporated herein by referencefor any and all purposes.

FIELD OF THE INVENTION

The present invention relates generally to solar cells and, inparticular, to an improved structure and manufacturing process for abifacial solar cell.

BACKGROUND OF THE INVENTION

Bifacial solar cells (BSC) may use any of a variety of different designsto achieve higher efficiencies than those typically obtained by aconventional, monofacial solar cell. One such design is shown in U.S.Pat. No. 5,665,175 which discloses a BSC configuration with first andsecond active regions formed on the front and back surfaces of the BSC,respectively, the two regions separated by a distance λ. The distance λallows a leakage current to flow between the first and second activeregions, thus allowing a solar cell panel utilizing such bifacial cellsto continue to operate even if one or more individual solar cells becomeshaded or defective.

U.S. Pat. No. 7,495,167 discloses an n⁺pp⁺ structure and a method ofproducing the same. In the disclosed structure, the p⁺ layer, formed byboron diffusion, exhibits a lifetime close to that of the initial levelof the substrate. In order to achieve this lifetime, the '167 patentteaches that after phosphorous gettering, the cell must be annealed at atemperature of 600° C. or less for one hour or more. In order to retainthe lifetime recovered by the phosphorous and low-temperature borngettering steps, the cell then undergoes a final heat treatment step inwhich the cell is fired at a temperature of around 700° C. or less forone minute or less.

U.S. Patent Application Publication No. 2005/0056312 discloses analternative technique for achieving two or more p-n junctions in asingle solar cell, the disclosed technique using transparent substrates(e.g., glass or quartz substrates). In one disclosed embodiment, the BSCincludes two thin-film polycrystalline or amorphous cells formed onopposing sides of a transparent substrate. Due to the design of thecell, the high temperature deposition of the absorber layers can becompleted before the low temperature deposition of the window layers,thus avoiding degradation or destruction of the p-n junctions.

Although there are a variety of BSC designs and techniques forfabricating the same, these designs and techniques tend to be relativelycomplex, and thus expensive. Accordingly, what is needed is a solar celldesign that achieves the benefits associated with bifacial solar cellswhile retaining the manufacturing simplicity of a monofacial solar cell.The present invention provides such a design.

SUMMARY OF THE INVENTION

The present invention provides a simplified manufacturing process andthe resultant bifacial solar cell (BSC), the simplified manufacturingprocess reducing manufacturing costs. In at least one embodiment of theinvention, a manufacturing method is provided that is comprised of thesteps of depositing a boron doped layer onto the back surface of ap-type silicon substrate, depositing a back surface dielectric over theboron doped layer, diffusing phosphorous onto the front surface of thesilicon substrate to form an n⁺ layer and a front surface junction,removing the phosphor-silicate glass formed during the diffusion step(e.g., by etching with HF), depositing a front surface passivation andAR dielectric layer onto the n⁺ layer, applying front and back surfacecontact grids, firing the front and back surface contact grids, andisolating the front surface junction, for example using a laser scriber.The front and back surface contact grid firing steps may be performedsimultaneously. Alternately, the back surface contact grid applying andfiring steps may be performed prior to, or after, the front surfacecontact grid applying and firing steps. The boron doped layer depositingstep can be formed by depositing a boron doped silicon dioxide layerusing CVD, depositing a boron doped polysilicon layer using CVD,depositing a boron doped amorphous silicon layer using PE-CVD, spraycoating a boric acid solution onto the back surface of the substrate,spray/wipe coating a boron-doped spin-on glass onto the back surface ofthe substrate, or by other means. The phosphorous diffusing step may beperformed at a temperature in the range of 825° C. to 890° C. for aduration of approximately 10 to 20 minutes.

In at least one embodiment of the invention, a bifacial solar cell (BSC)is provided that is comprised of a silicon substrate of a firstconductivity type with a front surface active region of a secondconductivity type and a back surface doped region of the firstconductivity type, dielectric layers deposited on the front surfaceactive region and on the back surface doped region, a front surfacecontact grid applied to the front surface passivation and AR dielectriclayer which alloys through the front surface dielectric to the activeregion during firing, a back surface contact grid applied to the backsurface dielectric layer which alloys through the back surfacedielectric to the back surface doped region during firing, and a grooveon the front surface of the silicon substrate, the groove isolating thefront surface junction. The silicon substrate may be comprised of p-typesilicon, the active region may be comprised of n⁺ material resultingfrom a phosphorous diffusion step, and the doped region may be comprisedof a boron dopant. The silicon substrate may be comprised of n-typesilicon, the active region may be comprised of p⁺ material resultingfrom a boron diffusion step, and the doped region may be comprised of aphosphorous dopant.

A further understanding of the nature and advantages of the presentinvention may be realized by reference to the remaining portions of thespecification and the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a preferred embodiment of a BSC in accordance withthe invention;

FIG. 2 illustrates the process flow for the BSC of FIG. 1; and

FIG. 3 illustrates an alternate process flow for the BSC of FIG. 1.

DESCRIPTION OF THE SPECIFIC EMBODIMENTS

FIG. 1 illustrates a cross-sectional view of a preferred bifacial solarcell (BSC) structure fabricated in accordance with the proceduredescribed in FIGS. 2 and 3. Silicon substrate 101 may be of either p- orn-type. In the exemplary device and process illustrated in FIGS. 1-3, ap-type substrate is used.

Initially, substrate 101 is prepared using any of a variety ofwell-known substrate preparatory processes (step 201). In general,during step 201 saw and handling induced damage is removed via anetching process, for example using a nitric and hydrofluoric (HF) acidmixture. After substrate preparation, the bottom surface of substrate101 is doped, thereby forming a back surface doped region 103 (step203). Region 103 is doped with the same doping type as substrate 101.Increasing the doping level of region 103, compared to substrate 101,lowers the contact resistance. Additionally, doped region 103 reducesback surface recombination and the effects of a positive potential inthe back surface insulator to attract minority carriers to the backsurface and thus away from the front surface collecting junction.

Region 103 can be formed using any of a variety of techniques. Exemplarytechniques include, but are not limited to, chemical vapor deposition(CVD), plasma enhanced CVD (PE-CVD), spray coating, and spin coating.Accordingly, and assuming a p-type substrate, region 103 can be formedby depositing a boron doped polysilicon layer using CVD; depositing aboron doped silicon dioxide or amorphous silicon layer using PE-CVD;spray/spin coating a boric acid solution or doped spin-on glass onto theback surface of substrate 101; or by other means.

After formation of region 103, a dielectric layer 105 is deposited onthe back surface of substrate 101, specifically on top of doped region103 as shown (step 205). Preferably layer 105 is comprised of eithersilicon nitride or silicon dioxide, preferably deposited at atemperature of 300° C. to 400° C., and has a thickness of approximately76 nanometers for silicon nitride or 100 nanometers for silicon dioxide.In an alternate embodiment, layer 105 is comprised of siliconoxynitride. In another alternate embodiment, layer 105 is comprised of adielectric stack, for example 70 nanometers of silicon nitride on 10nanometers of silicon dioxide or aluminum oxide.

After deposition of dielectric layer 105, phosphorous is diffused ontothe front surface of substrate 101, creating n⁺ layer 107 and a p-njunction at the interface of substrate 101 and n⁺ layer 107 (step 207).Preferably n⁺ layer 107 is formed using phosphoryl chloride (POCl₃),where the diffusion is performed at a diffusion temperature in the rangeof 825° C. to 890° C., preferably at a temperature of approximately 850°C., for 10 to 20 minutes in a nitrogen atmosphere (step 207). It will beappreciated that during the phosphorous diffusion step 207, boron fromregion 103 is diffused into the back surface of substrate 101 to form aback surface field (BSF). The phosphor-silicate glass (PSG) formedduring diffusion step 207 is then etched away, for example using ahydrofluoric (HF) etch at or near room temperature for 1 to 5 minutes(step 209). In the preferred embodiment, the front side junction has adepth of 0.3 to 0.6 microns and a surface doping concentration of about8×10²¹/cm³.

In step 211, a front surface passivation and anti-reflection (AR)dielectric layer 109 is deposited, layer 109 preferably beingapproximately 76 nanometers thick. In the exemplary embodiment, layer109 is comprised of silicon nitride or silicon oxynitride. Preferably,layer 109 is deposited at a temperature of 300° C. to 400° C.

After deposition of the dielectric layer 109, contact grids are appliedto the front and back surfaces of BSC 100 (step 213), for example usinga screen printing process. In the exemplary embodiment, front contactgrid 111 is comprised of silver while back contact grid 113 is comprisedof an aluminum-silver mixture. In the preferred embodiment, both thefront and back contact grids are aligned and use the same contact sizeand spacing, with electrodes being approximately 100 microns wide, 15microns thick and spaced approximately 2.5 millimeters apart. In atleast one alternate embodiment, the back contact grid uses a finerspacing in order to lessen resistance losses from lateral current flowin the substrate. Next, a contact firing step 213 is performed,preferably at a peak temperature of 750° C. for 3 seconds in air. As aresult of this process, contacts 111 alloy through passivation and ARdielectric coating 109 to n⁺ layer 107. Similarly, contacts 113 alloythrough dielectric coating 105 to layer 103. Lastly, the front junctionis isolated, for example using a laser scriber to form a groove on thefront cell surface around the periphery of the cell (step 217).

FIG. 3 illustrates an alternate process for fabricating cell 100. Asillustrated, this process is identical to that shown in FIG. 2, exceptthat the front surface and back surface contact grids are applied andfired separately, thereby allowing different firing conditions to beused for each grid. Preferably contact grid 113 is applied (step 301)and fired (step 303) first, followed by the application (step 305) andfiring (step 307) of front contact grid 111.

As previously noted, an n-type substrate may also be used with theinvention. In such an embodiment, an n-type dopant, such as phosphorous,is used for region 103 while a p-type material, such as boron, isdiffused into the front surface to form the p-n junction at theinterface of substrate 101 and diffused region 107.

As will be understood by those familiar with the art, the presentinvention may be embodied in other specific forms without departing fromthe spirit or essential characteristics thereof Accordingly, thedisclosures and descriptions herein are intended to be illustrative, butnot limiting, of the scope of the invention.

1-20. (canceled)
 21. A method of fabricating a bifacial solar cell(BSC), the method comprising the steps of: depositing a boron dopedlayer on a back surface of a p-type silicon substrate; depositing a backsurface dielectric onto said boron doped layer; diffusing phosphorousonto a front surface of said silicon substrate to form an n⁺ layer and afront surface junction; removing a phosphor-silicate glass (PSG) formedduring said phosphorous diffusing step; depositing a front surfacepassivation and anti-reflection (AR) dielectric layer onto said n⁺layer; applying a back surface contact grid; applying a front surfacecontact grid; firing said back surface contact grid; firing said frontsurface contact grid; and isolating said front surface junction.
 22. Themethod of claim 21, wherein said step of applying said back surfacecontact grid further comprises the step of screen printing said backsurface contact grid, and wherein said step of applying said frontsurface contact grid further comprises the step of screen printing saidfront surface contact grid.
 23. The method of claim 21, wherein saidfront surface junction isolating step further comprises the step offorming a groove on the front surface of the BSC with a laser scriber.24. The method of claim 21, wherein said steps of firing said back andfront surface contact grids are performed simultaneously.
 25. The methodof claim 21, wherein said step of firing said back surface contact gridis performed prior to said step of applying said front surface contactgrid.
 26. The method of claim 21, wherein said boron doped layerdepositing step further comprises the step of depositing a boron dopedsilicon dioxide layer using chemical vapor deposition.
 27. The method ofclaim 21, wherein said boron doped layer depositing step furthercomprises the step of depositing a boron doped silicon layer usingchemical vapor deposition.
 28. The method of claim 21, wherein saidboron doped layer depositing step further comprises the step ofdepositing a boron doped amorphous silicon layer using plasma enhancedchemical vapor deposition.
 29. The method of claim 21, wherein saidboron doped layer depositing step further comprises the step of sprayinga boric acid solution onto said back surface of said silicon substrate.30. The method of claim 21, wherein said boron doped layer depositingstep further comprises the step of spraying a boron doped spin-on glassonto said back surface of said silicon substrate.
 31. The method ofclaim 21, wherein said PSG removing step further comprises the step ofetching said front surface with a hydrofluoric etch.
 32. The method ofclaim 21, further comprising the step of selecting said dielectric fromthe group consisting of silicon nitride, silicon dioxide and siliconoxynitride.
 33. The method of claim 21, wherein said step of depositingsaid back surface dielectric onto said boron doped layer furthercomprises the step of depositing a dielectric stack onto said borondoped layer.
 34. The method of claim 32, further comprising the step ofselecting materials for said dielectric stack from the group consistingof silicon nitride, silicon dioxide and aluminum oxide.
 35. The methodof claim 21, wherein said phosphorous diffusing step is performed at atemperature of approximately 850° C. for a duration of approximately 10to 20 minutes.
 36. The method of claim 21, further comprising the stepof selecting said front surface passivation and AR dielectric layer fromthe group consisting of silicon nitride and silicon oxynitride.